Multiscale modeling of junction processing in fdsoi and finfet devices for 10 nm node technology and below

Resum

As device downscaling is on pace to reach the physical limits of miniaturization, new problems and challenges arise during the fabrication process. Consequently, potential replacements for conventional Si-based technologies have to be explored, such as 3D arquitectures (FinFETs) or the introduction of strain engineering techniques for further performance enhancement due to high mobility channels (SiGe as stressor material). Their manufacturing requirements involve highly activated and abrupt junction formation at the low temperature regime, and the Solid Phase Epitaxial Regrowth has been evidenced as the best option for processing advanced technology nodes of 10 nm and below. Relying on this context, the present manuscript is mainly focused at modeling the SPER of Si and SiGe alloys using a multiscale approach including: ab initio, Molecular Dynamics (MD), Lattice Kinetic Monte Carlo (LKMC), Object Kinetic Monte Carlo (OKMC) and Finite Element methods (FEM). The defect formation dependence on stress in Si is accounted by computing the strain pattern due to the volumetric expansion of the α-phase by using FEM methods, which are then evidenced as responsible for nucleation dislocation at the pinch off point of the two moving fronts during recrystallization by using MD simulations. Extracted results are finally extended into a LKMC model allowing to simulate realistic sample sizes, providing a physical explanation of the defect formation mechanisms and their strong dependence on the presence of strain patterns. Moreover, SiGe alloys are considered, and the Ge composition dependence of SPER activation energies is modeled by using MD, extracting an anomalous behavior as the profile does not vary monotonically between values of pure Si and Ge. Nudged Elastic Band calculations are performed to confirm the two-part behavior of the SPER activation energies: the SPER rate itself and a second extra term due to the bond length difference present in the alloy. Finally, as a novel application of strained SiGe layers, the SiGe channel FinFET devices are modeled in terms of defect formation when increasing the Ge content in the alloy.