Compact dc modeling of tunnel-fets

Laburpena

In the last five decades of semiconductor and integrated circuit (IC) development the metal-oxide-semiconductor field-effect transistor (MOSFET) has become the most important and technologically advanced semiconductor device. Due to its scalability, the MOSFET has been able to meet the needs of the chip designers for a steadily decreasing transistor size in order to achieve an increasing transistor density on a single chip. When coming to MOSFET channel lengths below 100 nm, the parasitic short-channel effects (SCEs) start to worse the MOSFET behavior. These effects have been counteracted with the introduction of multiple-gate FETs. Another important issue is the reduction of the supply voltage that also worsens the OFF-current of the MOSFETs due to the SCEs. One alternative to eliminate the OFF-current increase would be the reduction of the subthreshold slope of the MOSFET. Since the current transport in MOSFETs is based on the thermionic emission, the subthreshold slope at room temperature is limited to 60 mV/dec. For these reasons, the scientific community is consequently looking for an alternative to the MOSFET technology having a steeper switching behavior, a smaller supply voltage and a lower OFF-current. One promising candidate that offers all these advantages and additionally full CMOS compatibility, is the tunnel field-effect transistor (TFET) which is handled as a possible successor of the conventional MOSFET technology [1]. The TFET is basically a gated p-i-n diode and its current transport is based on the band-to-band (B2B) tunneling mechanism. For this reason, it is possible to achieve a subthreshold slope smaller than 60 mV/dec and simultaneously a low OFF-current. Since the TFET development is at its early stages and only a few research groups focus on the fabrication process, it is very important to investigate and enhance the TFET performance with the help of TCAD simulations. It is to say that TFETs having a subthreshold slope < 60 mV/dec have been fabricated but the resulting ON-current is still too low for a practical application [2]. In addition to the low ON-currents, the presence of traps at the source/drain-to-channel junctions and within the gate insulator material worsens the OFF-current and the subthreshold slope of the TFET due to trap-assisted tunneling (TAT). Hence, there is still a lot of work to do to improve the TFET technology. An equally important issue is the examination of the TFET behavior in simulating TFET-based ICs in terms of the TAT effect and the ambipolar behavior, which is a cause of the asymmetric doping of the source and drain region of the TFET. For this reason, a compact DC model for an n-type double-gate (DG) TFET is presented in this dissertation. It should be mentioned in advance that there are some objectives that a compact TFET model has to fulfil. At first, the model has to reproduce the device terminal current-voltage (I-V) characteristics over all regions of operation of interest. All modeling equations should be derived analytically and in closed-form to ensure a continuous and quick simulation of the device [3]. Furthermore, the modeling equations should be derived in a form that they can easily be implemented in the hardware description language Verilog-A. Due to the B2B tunneling and TAT, an accurate description of the electrostatic potential and the band diagram is mandatory to ensure a proper calculation of the tunneling probability. In order to take into account SCEs in the current calculations, the model equations should include 2D effects. In a second step the model should be verified by TCAD Sentaurus simulations for various device parameter setups and measurements of fabricated TFETs and thirdly the compact model continuity and flexibility should be proven in terms of basic TFET circuit simulations. The n-type compact DC model is derived on the basis of an analytical-numerical 2D DG TFET model presented in [4]. In order to obtain an accurate solution of the potential, the derivation of the compact electrostatics is done with the help of the 2D closed-form potential solution of the analytical-numerical model. Despite being a closed solution, it cannot be used for time-efficient Verilog-A implementation. Thus, the compact potential is separately approximated by suitable mathematical functions in the direction of x and y [5]. The potential along the x-axis in the source and drain region is approximated by a parabola and the channel potential follows approximately a rational function. The parameters to define the potential approximations are calculated with the help of the 2D analytical electrostatic solution. Applying the compact potential solution along the x-axis, it is possible to approximate the y-potential from gate to gate by a polynomial function. The exponent of this function is determined in dependency of the effect of inversion charges on the electrostatics. Since the 2D analytical solution is derived for the subthreshold regime of the TFET, the model is extended by an inversion charge based approach. Considering the first derivative of the potential in x and y direction, it is possible to find a compact electric field solution. The band diagram of the DG TFET is determined with the help of the compact potential solution along the x-axis. Due to high doping concentrations of the source and drain region, the band gap narrowing effect is considered in the calculations. Furthermore, the compact band diagram equations are suitable to take heterojunction TFETs into account [6]. In the next step of the model derivation, the tunneling probability for the B2B tunneling and the TAT effect is calculated by an area-equivalent WKB approach [6]. Here, the tunneling energy barrier is approximated with the help of a triangular energy profile, which has an equal area as the energy barrier defined by the band diagram. The tunneling distance, which is also derived on the basis of the band diagram, is used to find a compact expression of the area-equivalent energy triangle. Landauer’s tunneling formula is used to define the B2B tunneling generation rate (TGR) considering 2D effects in the direction of x and y within the channel region of the TFET. A compact expression is found by an approximation of the B2B TGR along the x-axis for any y-position with a Gaussian distribution function. This approximation allows for a closed-form integration in order to obtain the current density along the y-axis. Regarding TAT, the generation formula is rearranged by combining Landauer’s formula with the TAT model of Hurkx [7]. A closed-form and integrable approximation of the TAT generation rate is again found by a Gaussian distribution function. The current density along the y-axis needs to be approximated and this is also done with the help of a Gaussian distribution which defines the current density in the first half of the channel. The integration of both the B2B tunneling and TAT current density leads to the device current of the TFET. The device current solution is implemented in Verilog-A to verify the modeling approach. The compact model verification is separated into two steps. In the first one, the accuracy of the compact model is proven by TCAD Sentaurus simulation data [8]. After that the compact model is verified by measurements of complementary fabricated TFETs [9]. The compact modeling parts like the electrostatic potential, the band diagram and the electric field are separately calculated and compared with extracted data from TCAD simulations. TCAD simulations are performed for various bias conditions and device parameters like doping concentration, device dimensions and source materials. The compact model shows a good agreement with the simulations in dependency of x and y. With the help of the band diagram it is possible to illustrate the tunneling energy barrier triangle calculated by the AE WKB approach and compare the results with a quasi-2D WKB approach presented in [10]. The compact and numerically robust AE WKB approach offers a better match in comparison to the quasi-2D WKB approximation regarding the resulting tunneling barrier height for various bias conditions and source materials. After that the B2B TGR along the x-axis and for various y-positions is verified by TCAD data and shows also a good match for different bias conditions and source materials. An important requirement in compact modeling is that the DC model has to reproduce the current I-V characteristics of the device and this is done to demonstrate the flexibility of the modeling approach. At first, the compact model is verified by TCAD simulations of the current output curve and its first two derivatives for various bias conditions. Secondly, TCAD simulations are performed for various applied bias conditions and device parameters like geometrical dimensions, materials and doping concentrations in order to prove the accuracy of the compact model in terms of the transfer I-V characteristics. All simulation results, even the first two derivatives, match very well with the extracted TCAD data. Herewith, a good scalability of the model is demonstrated considering the same extracted model parameters for various device dimensions and gate insulator materials. A change in the source material offers also a good agreement of the compact model and the TCAD simulation data. After the verification by TCAD simulations the compact model is adapted to complementary fabricated nanowire gate-all-around TFETs [9]. In this case, the p-type model is emulated from the n-type modeling approach. The validity of the compact model is proven with the help of the measured transfer I-V curves for various drain-source voltages for both the n- and p-type TFET. Using the model parameters extracted for the fabricated TFETs, it is possible to simulate the DC behavior of a single-stage TFET inverter and verify the results by measurements of the voltage transfer characteristics. The simulations for various supply voltages stay in a good agreement with the measured data. The parasitic TAT effect and the ambipolar behavior of the TFET are very well reproduced by the compact DC model. Using the same model parameter set, a realistic DC simulation of a TFET-based SRAM cell is performed to analyze the resulting static noise margin of the cell. In the last circuit simulation, the DC model is extended by an AC model of the intrinsic capacitances in TFETs which allows for a transient simulation of an 11-stage ring oscillator. All single TFET and TFET-based circuit simulations show the numerical stability, continuity and flexibility of the presented compact modeling approach. In order to conclude this dissertation, a compact DC model for a DG TFET is introduced which fulfils the aforementioned required objectives. All equations are analytically solved and suitable for an implementation in Verilog-A. Simulations using the Verilog-A model demonstrated the continuity and flexibility of the approach. [1] A. C. Seabaugh and Q. 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Kloes, “Area equivalent WKB compact modeling approach for tunneling probability in hetero-junction TFETs including ambipolar behavior,” International Journal of Microelectronics and Computer Science, vol. 9, pp. 47-59, Dec. 2018. [7] F. Horst, A. Farokhnejad, B. Iniguez , and A. Kloes, “Closed-form modeling approach of trap-assisted tunneling current for use in compact TFET models,” in 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", pp. 81-86, IEEE, June 2019. [8] Synopsys, Inc., Sentaurus Device User Guide. Version O-2018.06, June 2018. [9] G. Luong, S. Strangio, A. Tiedemannn, S. Lenk, S. Trellenkamp, et al., “Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages,” Solid-State Electronics, vol. 115, pp. 152-159, Jan. 2016. [10] M. Graef, T. Holtij, F. Hain, A. Kloes, and B. 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