Publications dans lesquelles il/elle collabore avec Martin Margala (19)

2017

  1. A high performance Full Adder based on Ballistic Deflection Transistor technology

    Proceedings - IEEE International Symposium on Circuits and Systems

2016

  1. Ballistic deflection transistor very high frequency modeling

    Device Research Conference - Conference Digest, DRC

  2. Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations

    IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, Núm. 12, pp. 2236-2244

  3. Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

  4. Monte Carlo modeling of ultra-fast operating Ballistic Deflection Transistor

    Proceedings of the 25th Biennial Lester Eastman Conference on High Performance Devices, LEC 2016

2015

  1. Exploration of digital latch design using ballistic deflection transistors-Modeling and simulation

    2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

  2. Optimization of Ballistic Deflection Transistors by Monte Carlo Simulations

    Journal of Physics: Conference Series

  3. Study of surface charges in ballistic deflection transistors

    Nanotechnology, Vol. 26, Núm. 48

2013

  1. Ballistic deflection transistor: Geometry dependence and boolean operations

    Proceedings of the 2013 Spanish Conference on Electron Devices, CDE 2013

  2. Ballistic deflection transistor: Geometry dependence and boolean operations

    Proceedings of the 2013 Spanish Conference on Electron Devices (Universidad de Valladolid)

2012

  1. Effects of a high-k dielectric on the performance of III-V ballistic deflection transistors

    IEEE Electron Device Letters, Vol. 33, Núm. 8, pp. 1120-1122

2011

  1. Exploring digital logic design using ballistic deflection transistors through monte carlo simulations

    IEEE Transactions on Nanotechnology, Vol. 10, Núm. 6, pp. 1337-1346

  2. General purpose logic gate using ballistic nanotransistors

    Proceedings of the IEEE Conference on Nanotechnology

  3. Nonlinear electron properties of an InGaAs/InAlAs-based ballistic deflection transistor: Room temperature DC experiments and numerical simulations

    Solid-State Electronics, Vol. 56, Núm. 1, pp. 120-129

  4. Realization of logic operations through optimized ballistic deflection transistors

    Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

2010

  1. A study of geometry effects on the performance of ballistic deflection transistor

    IEEE Transactions on Nanotechnology, Vol. 9, Núm. 6, pp. 723-733

  2. High performance digital circuit design using ballistic nano-electronics

    Midwest Symposium on Circuits and Systems

  3. Sub-THz frequency analysis in nano-scale devices at room temperature

    Device Research Conference - Conference Digest, DRC

  4. Topology impact on the room temperature performance of THz-range ballistic deflection transistors

    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI